Integrated circuits (ICs) are small electronic components that are made out of semiconductor materials, metals, and dielectrics. To route an electrical signal, ICs typically use interconnects and vias. The IC industry has developed various interconnect technologies with high aspect-ratio filled plugs, including stacked via, for advanced multi-level IC processing. Such technologies include dual-damascene on an interlayer dielectric (ILD), various metallization processes, chemical and physical vapor deposition (CVD/PVD), copper plating, and chemical-mechanical polishing (CMP) of interconnect metal.
Additionally, several specific techniques have been described for generating high aspect-ratio interconnects in III-V compound semiconductor ICs. Such techniques were described by Shigeki Wada et al., in a publication entitled, “0.2 μm Fully-Aligned Y-Shaped gate HJFET's with Reduced Gate-Fringing Capacitance Fabricated Using Collimated Sputtering and Electroless Au-Plating,” in IEEE Transactions on Electron Devices, vol. 45, no. 8, August, 1998, pp. 1656-1662. Another technique is described by M. Y. Chan and T. C. Lo, in a publication entitled, “Electrochemical Planarization By Selective Electroplating For Embedded Gold Wiring In The Sub-Micron Range,” in IEEE Region 10 International Conference on Microelectronics and VLSI, pp. 287-290, 1995. Yet another technique was described by M. Hirano et al., in a publication entitled, “Submicrometer Gold Interconnect Wiring by Sidewall Electroplating Technology,” in Jpn J. Apply. Phys. 33, 1994, L553-L555.
The first two papers have several features in common. More specifically, they describe etching into SiO2 to form a trench for areas needed to be plated up. They also both describe plating a seed layer and trench filling with a photoresist, followed by etch-back to remove or oxidize the seed layer outside of the trenches. Finally, they describe photoresist removal and gold (Au) plating.
The paper by Shigeki Wada et al., about the 0.2 μm Y-shaped gate plating process, describes forming the lower part of the Y such that it is narrow with an aspect ratio of 1:1 (deposition of the seed layer depends on a special sputtering system with 2:1 collimating tubes). The upper part of the Y-shape plated gate is curved (or bent) laterally as the result from the shape of the seed layer after its etch-back (after photoresist is used to fill the trench). Although it is fitted well for Y-shaped gates, such a shape is not sufficient (with respect to dimension control and aspect ratio) in via for interconnects in high density and complex ICs.
The second paper, by M. Y. Chan and T. C. Lo, describes a process that depends on controlling the removal of a top seed layer and passivation (oxidation) of the seed metal surface to define areas for plating. The authors also indicated that thoroughly removing the filled photoresist in the trench after the oxidization, before plating, is also crucial.
The third paper, by M. Hirano et al., describes a copper plug-like process employing electrochemical planarization. As described, the seed layer is grown on the inside and outside of trenches to follow the contour of the trenches. The seed layer is plated to reach above the top of the trenches. The “over-plated” trenches are then removed by electrochemical planarization. While operational as via interconnect, such trenches do not provide for stacking, as multiple stacked layers would become increasingly large in size.
Plating into a trenched via formed by an interlayer dielectric (ILD) etch is a typical interconnect technology that is used in III-V compound semiconductor ICs. Such interconnects usually consume more area than designers prefer and can be a limiting factor in performance of complex ICs with advanced devices. The differences in interconnect technology can be crucial because interconnect technology with low parasitic values and high density values is necessary for a high-speed, low power IC. However, in III-V compound semiconductor ICs, high-speed scaled device performance has been significantly improved. Nevertheless, old interconnect technology remains, unlike in SiGe hetero-junction bipolar transistor-based (HBT-based) IC technology. High performance InP-based HBTs are known to have great advantages in high-speed IC applications. However, more compact circuits with less parasitics can save more power, especially in complex circuits.
For example, via plugs with a high aspect ratio can lower via and interconnect resistance, and increase current density, especially for scaled (into sub-micron region) vias. As described above, typical existing IC technology uses a trench style via to connect interconnect metal layers.
Typical steps for plating of trenched via are shown in FIGS. 1-3. As shown in FIG. 1, trenches are first formed by Inductance Coupled Plasma (ICP) etching the ILD to expose metal contacts where interconnects are needed. Then, a seed layer for electroplating is deposited. As shown in FIG. 2, the trench is plated to form the plated via. The sidewall of the trenched via has a sloped profile (instead of vertical) as a result of the ICP etch. The sloped trench causes the via to have a wider top than bottom and decreases the aspect-ratio of plated via. As shown FIG. 3, the photoresist is removed to expose the top of the plated via. As evident in the figures, the sloped trench causes a dent on top of the plated feature, which is not planarized enough for building another via on top of it with tight control of dimension.
Thus, current trench style vias provide dimension aspect ratios (height to width of via) less than (<) or approximately equal to (˜) 1. Such traditional via sidewalls curve near the top and the top becomes wider than its bottom. As discussed above, after plating, there is a dip on the top of via. Therefore, the upper level inter level dielectric layer cannot be truly planar near via regions. Because the planarization dielectric layer is only marginally planar, it is difficult to build a stacked via on an existing via with good dimensional control. The end results, beside extra acreage, are extra parasitics and lack of flexibility in circuit design, especially in complex ICs like direct digital synthesizers (DDSs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs).
Therefore, a continuing need exits for smaller interconnects that feature dimension control (higher aspect-ratio) and the capability of using stacked via (with reduced acreage and parasitics) with additional interconnect levels for increasing circuit design.